-----------------------------------------------
-- Project		: ECE 251 FINAL PROJECT
-- Author 		: Mahmut Yilmaz
-- Last Modified: 04/01/2007
-----------------------------------------------

LIBRARY ieee;
USE ieee.std_logic_1164.all;
USE work.all;

ENTITY dflop IS
	PORT (	clock			: IN  STD_LOGIC;	-- PosEdge Clock used	
			reset			: IN  STD_LOGIC;	-- Resets the flop to 0, active HIGH
			set				: IN  STD_LOGIC;	-- Sets the flop to 1, active HIGH
			input			: IN  STD_LOGIC;	-- Flop input
      		q	 			: OUT STD_LOGIC 	-- Flop output
			);
END dflop;

ARCHITECTURE behav OF dflop IS
BEGIN
	PROCESS (reset, set, clock)
	BEGIN
		IF reset = '1' THEN
			q <= '0';
		ELSIF set = '1' THEN
			q <= '1';
		ELSIF (clock'EVENT AND clock='1') THEN -- @ PosEdge Clock
			q <= input;
		END IF;
	END PROCESS;
END behav;
